//
// 鼐屻偺撪晹港影霓(栺16MHz)偐傜
// 12MHz偺奜晅偗悈徎傪巊偭偨PLL影霓(48MHz)傊偺愗傝懼偊
//
void Init_Clock()
{
  MCGC2 = MCGC2_HGO_MASK
    | MCGC2_EREFS_MASK
    | MCGC2_RANGE_MASK
    | MCGC2_ERCLKEN_MASK;
  while (MCGSC_OSCINIT == 0)
    ;
  MCGC1 = (2<<6) // external reference clock.
      | (3<<3);  // RDIV = 3 : 12MHz/8=1.5 MHz
  while ((MCGSC_IREFST != 0) || (MCGSC_CLKST != 2))

  // FBE  PBE (PLL bypassed internal) 影霓偵堏峴
  MCGC3=MCGC3_PLLS_MASK
    | (8<<0); // multiply by 32 -> 1.5MHz*32=48MHz
  while((MCGSC_PLLST != 1) || (MCGSC_LOCK != 1))
    ;
// PBE影霓偐傜PEE 
// (PLL enabled external mode)
// 影霓偵堏峴
 MCGC1 = (0<<6) //PLL or FLL Clock
  | (3<<3); // 12MHz/8=1.5 MHz
 while(MCGSC_CLKST !=3)
    ;
}
