Synthesis and Ngdbuild Report
#Build: Synplify for Lattice 9.6L1, Build 069R, Nov 3 2008
#install: D:\ISPTOOLS7_2_STRT\synpbase
#OS: Windows XP 5.1
#Hostname: OPTIMIST-001
#Implementation: mfpga_lat
#Sun Apr 26 01:04:22 2009
$ Start of Compile
#Sun Apr 26 01:04:22 2009
Synplicity VHDL Compiler, version 1.0, Build 020R, built Nov 5 2008
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
@N: CD720 :"D:\ISPTOOLS7_2_STRT\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
Top entity isn't set yet!
VHDL syntax check successful!
@N: CD630 :"E:\mfpga_lat\hdl\mod_top.vhd":21:7:21:16|Synthesizing work.module_top.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_uart_tx.vhd":21:7:21:20|Synthesizing work.module_txblock.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_freq_div.vhd":26:7:26:21|Synthesizing work.module_freq_div.behavioral
Post processing for work.module_freq_div.behavioral
Post processing for work.module_txblock.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":20:7:20:26|Synthesizing work.module_wavegenerator.behavioral
@N: CD364 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":86:4:86:20|Removed redundant assignment
@N: CD630 :"E:\mfpga_lat\hdl\sintable.vhd":26:7:26:21|Synthesizing work.module_sintable.behavioral
@W: CG296 :"E:\mfpga_lat\hdl\sintable.vhd":4173:16:4173:22|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\mfpga_lat\hdl\sintable.vhd":4175:6:4175:14|Referenced variable sysrst_in is not in sensitivity list
@W: CG296 :"E:\mfpga_lat\hdl\sintable.vhd":4183:14:4183:20|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\mfpga_lat\hdl\sintable.vhd":4185:6:4185:14|Referenced variable sysrst_in is not in sensitivity list
@W: CG296 :"E:\mfpga_lat\hdl\sintable.vhd":4201:14:4201:20|Incomplete sensitivity list - assuming completeness
@W: CG290 :"E:\mfpga_lat\hdl\sintable.vhd":4203:6:4203:14|Referenced variable sysrst_in is not in sensitivity list
Post processing for work.module_sintable.behavioral
@W: CL170 :"E:\mfpga_lat\hdl\sintable.vhd":4175:1:4175:2|Pruning bit <0> of dly1_phase_adrs(1 downto 0) - not in use ...
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <14> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <13> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <12> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <11> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <10> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <9> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <8> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <7> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <6> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <5> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <4> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <3> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <2> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <1> of reg_sin_out2(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\sintable.vhd":4203:1:4203:2|Pruning Register bit <0> of reg_sin_out2(15 downto 0)
Post processing for work.module_wavegenerator.behavioral
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <7> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <6> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <5> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <4> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <3> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <2> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <1> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Pruning bit <0> of wave_sawtooth_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <7> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <6> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <5> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <4> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <3> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <2> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <1> of wave_triangle_value(15 downto 0) - not in use ...
@W: CL170 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Pruning bit <0> of wave_triangle_value(15 downto 0) - not in use ...
@N: CD630 :"E:\mfpga_lat\hdl\mod_pushsw_sync4.vhd":27:7:27:25|Synthesizing work.module_pushsw_sync4.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_pushsw_sync.vhd":28:7:28:24|Synthesizing work.module_pushsw_sync.behavioral
Post processing for work.module_pushsw_sync.behavioral
Post processing for work.module_pushsw_sync4.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_7seg_x4.vhd":25:7:25:20|Synthesizing work.module_7seg_x4.behavioral
@N: CD630 :"E:\mfpga_lat\hdl\mod_7seg.vhd":26:7:26:17|Synthesizing work.module_7seg.behavioral
Post processing for work.module_7seg.behavioral
Post processing for work.module_7seg_x4.behavioral
Post processing for work.module_top.behavioral
@W: CL189 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":79:1:79:2|Register bit AddressStep_adder(0) is always 0, optimizing ...
@W: CL189 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":79:1:79:2|Register bit AddressStep_adder(1) is always 0, optimizing ...
@W: CL171 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":79:1:79:2|Pruning Register bit <1> of AddressStep_adder(15 downto 0)
@W: CL171 :"E:\mfpga_lat\hdl\mod_wavegen.vhd":79:1:79:2|Pruning Register bit <0> of AddressStep_adder(15 downto 0)
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Apr 26 01:04:23 2009
###########################################################]
Synplicity Generic Technology Mapper, Version 9.4.2, Build 061R, Built Nov 25 2008 09:10:23
Copyright (C) 1994-2008, Synplicity Inc. All Rights Reserved
Product Version Version 9.6L1
@W: BN246 |Failed to find top level module 'work.Module_TOP' as specified in project file
@N: MF249 |Running in 32-bit mode.
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: MO106 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Found ROM, 'int_Seg_Data_out[6:0]', 16 words by 7 bits
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: MO106 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Found ROM, 'int_Seg_Data_out[6:0]', 16 words by 7 bits
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: MO106 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Found ROM, 'int_Seg_Data_out[6:0]', 16 words by 7 bits
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: FA239 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Rom int_Seg_Data_out[6:0] mapped in logic.
@N: MO106 :"e:\mfpga_lat\hdl\mod_7seg.vhd":42:21:42:22|Found ROM, 'int_Seg_Data_out[6:0]', 16 words by 7 bits
Finished RTL optimizations (Time elapsed 0h:00m:01s; Memory used current: 108MB peak: 110MB)
@N:"e:\mfpga_lat\hdl\mod_freq_div.vhd":46:1:46:2|Found counter in view:work.Module_Freq_div_u_FreqDiv_Seg7(behavioral) inst internal_counter[23:0]
@N:"e:\mfpga_lat\hdl\mod_freq_div.vhd":46:1:46:2|Found counter in view:work.Module_Freq_div(behavioral) inst internal_counter[23:0]
@N:"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":69:1:69:2|Found counter in view:work.Module_PUSHsw_sync_u_SW1(behavioral) inst reg_MASK_counter[6:0]
@N:"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":69:1:69:2|Found counter in view:work.Module_PUSHsw_sync_u_SW2(behavioral) inst reg_MASK_counter[6:0]
@N:"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":69:1:69:2|Found counter in view:work.Module_PUSHsw_sync_u_SW3(behavioral) inst reg_MASK_counter[6:0]
@N:"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":69:1:69:2|Found counter in view:work.Module_PUSHsw_sync(behavioral) inst reg_MASK_counter[6:0]
@N:"e:\mfpga_lat\hdl\mod_freq_div.vhd":46:1:46:2|Found counter in view:work.Module_Freq_div_u_TxCLKgen(behavioral) inst internal_counter[23:0]
Dissolving instances of view:work.Module_Freq_div_u_FreqDiv_Seg7(behavioral) before factorization cost=105, pathcnt=1
Dissolving instances of view:work.Module_Freq_div(behavioral) before factorization cost=105, pathcnt=1
Dissolving instances of view:work.module_7seg_u_7Seg_digit_1(behavioral) before factorization cost=64, pathcnt=1
Dissolving instances of view:work.module_7seg_u_7Seg_digit_2(behavioral) before factorization cost=64, pathcnt=1
Dissolving instances of view:work.module_7seg_u_7Seg_digit_3(behavioral) before factorization cost=64, pathcnt=1
Dissolving instances of view:work.module_7seg(behavioral) before factorization cost=64, pathcnt=1
Dissolving instances of view:work.module_7seg_x4(behavioral) before factorization cost=256, pathcnt=1
Dissolving instances of view:work.Module_PUSHsw_sync_u_SW1(behavioral) before factorization cost=75, pathcnt=1
Dissolving instances of view:work.Module_PUSHsw_sync_u_SW2(behavioral) before factorization cost=75, pathcnt=1
Dissolving instances of view:work.Module_PUSHsw_sync_u_SW3(behavioral) before factorization cost=75, pathcnt=1
Dissolving instances of view:work.Module_PUSHsw_sync(behavioral) before factorization cost=75, pathcnt=1
Dissolving instances of view:work.Module_PUSHsw_sync4(behavioral) before factorization cost=300, pathcnt=1
Dissolving instances of view:work.module_sintable(behavioral) before factorization cost=245, pathcnt=1
Dissolving instances of view:work.Module_WaveGenerator(behavioral) before factorization cost=606, pathcnt=1
Dissolving instances of view:work.Module_Freq_div_u_TxCLKgen(behavioral) before factorization cost=105, pathcnt=1
Dissolving instances of view:work.Module_TxBlock(behavioral) before factorization cost=371, pathcnt=1
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Removing sequential instance u_mdl_WaveGen.wave_sawtooth_value[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":119:1:119:2|Removing sequential instance u_mdl_WaveGen.wave_sawtooth_value[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Removing sequential instance u_mdl_WaveGen.wave_triangle_value[9] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":96:1:96:2|Removing sequential instance u_mdl_WaveGen.wave_triangle_value[8] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":146:1:146:2|Removing sequential instance u_mdl_WaveGen.WaveOut[1] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_wavegen.vhd":146:1:146:2|Removing sequential instance u_mdl_WaveGen.WaveOut[0] of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4167:1:4167:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.rom_data[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\sintable.vhd":4185:1:4185:2|Removing sequential instance u_mdl_WaveGen.u_mdl_sintable.reg_sin_out1[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW4.PUSHSW_out of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW4.PUSHSW_L_edge of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW3.PUSHSW_out of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW3.PUSHSW_L_edge of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW2.PUSHSW_out of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW2.PUSHSW_L_edge of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW1.PUSHSW_out of view:UNILIB.FDR(PRIM) because there are no references to its outputs
@N: BN116 :"e:\mfpga_lat\hdl\mod_pushsw_sync.vhd":97:1:97:2|Removing sequential instance u_PUSHSW_sync.u_SW1.PUSHSW_L_edge of view:UNILIB.FDRE(PRIM) because there are no references to its outputs
Finished factoring (Time elapsed 0h:00m:01s; Memory used current: 110MB peak: 111MB)
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 111MB)
Starting Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 111MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 111MB)
Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:02s; Memory used current: 109MB peak: 111MB)
@N: FX214 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Generating ROM u_mdl_WaveGen.u_mdl_sintable.sin_out[14:0]
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_9 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_8 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_7 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_6 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_5 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_4 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_3 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_2 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_1 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3840_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3584_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3328_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out3072_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2816_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2560_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2304_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out2048_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1792_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1536_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1280_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out1024_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out768_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out512_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out256_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
@N: BN114 :"e:\mfpga_lat\hdl\sintable.vhd":63:1:63:4|Removing instance u_mdl_WaveGen.u_mdl_sintable.sin_out0_0 of black_box view:LUCENT.ROM256X1(PRIM) because there are no references to its outputs
Starting Early Timing Optimization (Time elapsed 0h:00m:05s; Memory used current: 115MB peak: 116MB)
Finished Early Timing Optimization (Time elapsed 0h:00m:06s; Memory used current: 115MB peak: 116MB)
Finished preparing to map (Time elapsed 0h:00m:06s; Memory used current: 115MB peak: 116MB)
Finished technology mapping (Time elapsed 0h:00m:06s; Memory used current: 115MB peak: 117MB)
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:06s -2.69ns 352 / 219
2 0h:00m:06s -2.69ns 352 / 219
3 0h:00m:06s -2.56ns 353 / 219
4 0h:00m:06s -2.56ns 353 / 219
5 0h:00m:06s -2.56ns 353 / 219
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:07s -1.74ns 351 / 219
Timing driven replication report
No replication required.
2 0h:00m:07s -1.74ns 351 / 219
3 0h:00m:07s -1.74ns 351 / 219
4 0h:00m:07s -1.74ns 351 / 219
------------------------------------------------------------
Timing driven replication report
No replication required.
Timing driven replication report
No replication required.
Pass CPU time Worst Slack Luts / Registers
------------------------------------------------------------
1 0h:00m:07s -1.74ns 351 / 219
Timing driven replication report
No replication required.
2 0h:00m:07s -1.74ns 351 / 219
3 0h:00m:07s -1.74ns 351 / 219
4 0h:00m:07s -1.74ns 351 / 219
------------------------------------------------------------
Net buffering Report for view:work.Module_TOP(behavioral):
No nets needed buffering.
@N: MF322 |Retiming summary: 0 registers retimed to 0
##### BEGIN RETIMING REPORT #####
Retiming summary : 0 registers retimed to 0
Original and Pipelined registers replaced by retiming :
None
New registers created by retiming :
None
##### END RETIMING REPORT #####
Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:07s; Memory used current: 115MB peak: 117MB)
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":217:19:217:20|Removing instance g0_7, because it is equivalent to instance Seg7_Digit3_Value[0]
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":214:19:214:20|Removing instance g0_3, because it is equivalent to instance g0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":214:19:214:20|Removing instance g0_9, because it is equivalent to instance g0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":217:19:217:20|Removing instance g0_1, because it is equivalent to instance u_7Seg_digit_1.u_7Seg_digit_3.int_Seg_Data_out_6_0_.g1_0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":217:19:217:20|Removing instance g0_8, because it is equivalent to instance u_7Seg_digit_1.u_7Seg_digit_3.int_Seg_Data_out_6_0_.g1_0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":214:19:214:20|Removing instance g0_6, because it is equivalent to instance g0_0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":214:19:214:20|Removing instance g0_4, because it is equivalent to instance g0_0
@W: BN132 :"e:\mfpga_lat\hdl\mod_top.vhd":214:19:214:20|Removing instance g0_10, because it is equivalent to instance g0_0
Found clock Module_TOP|SysCLK_in with period 5.00ns
##### START OF TIMING REPORT #####[
# Timing Report written on Sun Apr 26 01:04:32 2009
#
Top view: Module_TOP
Requested Frequency: 200.0 MHz
Wire load mode: top
Paths requested: 3
Constraint File(s):
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..
Performance Summary
*******************
Worst slack in design: -2.059
Requested Estimated Requested Estimated Clock Clock
Starting Clock Frequency Frequency Period Period Slack Type Group
----------------------------------------------------------------------------------------------------------------------------
Module_TOP|SysCLK_in 200.0 MHz 155.6 MHz 5.000 6.427 -1.427 inferred Inferred_clkgroup_0
System 200.0 MHz 141.7 MHz 5.000 7.059 -2.059 system default_clkgroup
============================================================================================================================
Clock Relationships
*******************
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
-----------------------------------------------------------------------------------------------------------------------------------
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
-----------------------------------------------------------------------------------------------------------------------------------
Module_TOP|SysCLK_in Module_TOP|SysCLK_in | 5.000 -1.427 | No paths - | No paths - | No paths -
===================================================================================================================================
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
----------------------------------------------------------------------------------
DIPSW_in[1] System (rising) NA 0.000 -2.059
DIPSW_in[2] System (rising) NA 0.000 -0.178
DIPSW_in[3] System (rising) NA 0.000 3.024
DIPSW_in[4] System (rising) NA 0.000 2.858
PORT_in[4] System (rising) NA 0.000 -1.293
PORT_in[5] System (rising) NA 0.000 -1.857
PORT_in[6] System (rising) NA 0.000 -1.865
PORT_in[7] System (rising) NA 0.000 -1.906
PUSHSW_in[1] System (rising) NA 0.000 3.431
PUSHSW_in[2] System (rising) NA 0.000 3.431
PUSHSW_in[3] System (rising) NA 0.000 3.431
PUSHSW_in[4] System (rising) NA 0.000 3.431
SysCLK_in NA NA NA NA NA
nSysRST_in System (rising) NA 0.000 1.051
==================================================================================
Output Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
------------------------------------------------------------------------------------------------------
PORT_out[2] System (rising) NA 6.304 5.000
PORT_out[3] System (rising) NA 6.304 5.000
PORT_out[4] System (rising) NA 6.296 5.000
PORT_out[5] System (rising) NA 6.296 5.000
PORT_out[6] System (rising) NA 6.296 5.000
PORT_out[7] System (rising) NA 6.296 5.000
SEG7_Digit1_out[1] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[2] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[3] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[4] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[5] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[6] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[7] Module_TOP|SysCLK_in (rising) NA 4.622 5.000
SEG7_Digit1_out[8] NA NA NA NA NA
SEG7_Digit2_out[1] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[2] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[3] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[4] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[5] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[6] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[7] Module_TOP|SysCLK_in (rising) NA 4.630 5.000
SEG7_Digit2_out[8] NA NA NA NA NA
SEG7_Digit3_out[1] System (rising) NA 6.304 5.000
SEG7_Digit3_out[2] System (rising) NA 6.304 5.000
SEG7_Digit3_out[3] System (rising) NA 6.304 5.000
SEG7_Digit3_out[4] System (rising) NA 6.560 5.000
SEG7_Digit3_out[5] System (rising) NA 7.059 5.000
SEG7_Digit3_out[6] System (rising) NA 6.304 5.000
SEG7_Digit3_out[7] System (rising) NA 6.304 5.000
SEG7_Digit3_out[8] NA NA NA NA NA
SEG7_Digit4_out[1] System (rising) NA 6.296 5.000
SEG7_Digit4_out[2] System (rising) NA 6.296 5.000
SEG7_Digit4_out[3] System (rising) NA 6.296 5.000
SEG7_Digit4_out[4] System (rising) NA 6.296 5.000
SEG7_Digit4_out[5] System (rising) NA 6.296 5.000
SEG7_Digit4_out[6] System (rising) NA 6.296 5.000
SEG7_Digit4_out[7] System (rising) NA 6.296 5.000
SEG7_Digit4_out[8] NA NA NA NA NA
TxD_out Module_TOP|SysCLK_in (rising) NA 3.722 5.000
nDAC_ENB NA NA NA NA NA
nTxD_Ready Module_TOP|SysCLK_in (rising) NA 3.722 5.000
======================================================================================================
##### END OF TIMING REPORT #####]
---------------------------------------
Resource Usage Report
Part: lfxp2_5e-6
Register bits: 219 of 4752 (5%)
PIC Latch: 0
I/O cells: 55
Details:
CCU2B: 68
FD1P3AX: 14
FD1P3BX: 1
FD1P3DX: 19
FD1P3IX: 23
FD1S3AX: 105
FD1S3BX: 2
FD1S3DX: 15
FD1S3IX: 34
GSR: 1
IB: 14
IFS1P3IX: 4
INV: 2
OB: 41
OFS1P3BX: 1
OFS1P3DX: 1
ORCALUT4: 341
PFUMX: 9
PUR: 1
ROM256X1: 37
VHI: 1
VLO: 1
Finished restoring hierarchy (Time elapsed 0h:00m:07s; Memory used current: 115MB peak: 117MB)
Writing Analyst data base E:\mfpga_lat\Module_TOP.srm
@N: MF203 |Set autoconstraint_io
Finished Writing Netlist Databases (Time elapsed 0h:00m:08s; Memory used current: 115MB peak: 117MB)
Writing EDIF Netlist and constraint files
Version 9.6L1
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:08s; Memory used current: 118MB peak: 119MB)
Writing Verilog Simulation files
Finished Writing Verilog Simulation files (Time elapsed 0h:00m:08s; Memory used current: 119MB peak: 119MB)
Writing VHDL Simulation files
Finished Writing VHDL Simulation files (Time elapsed 0h:00m:08s; Memory used current: 119MB peak: 119MB)
Mapper successful!
Process took 0h:00m:09s realtime, 0h:00m:08s cputime
# Sun Apr 26 01:04:33 2009
###########################################################]
Generated from the file 'E:\MFPGA_LAT\Module_TOP.srf'