Lattice Mapping Report File for Design 'Module_TOP'


Design Information

Command line:   D:\ispTOOLS7_2_STRT\ispfpga\bin\nt\map.exe -a LatticeXP2 -p
     LFXP2-5E -t TQFP144 -s 6 top.ngd -o top_map.ncd -mp top.mrp top.lpf
Target Vendor:  LATTICE
Target Device:  LFXP2-5ETQFP144
Target Speed:   6
Mapper:  mg5a00,  version:  ispLever_v72_SP1_Build (24)
Mapped on:  04/26/09  01:04:40


Design Summary
   Number of registers:    219
      PFU registers:    213
      PIO registers:    6
   Number of SLICEs:           472 out of  2376 (20%)
      SLICEs(logic/ROM):       472 out of  1971 (24%)
      SLICEs(logic/ROM/RAM):     0 out of   405 (0%)
          As RAM:            0 out of   405 (0%)
          As Logic/ROM:      0 out of   405 (0%)
   Number of logic LUT4s:     583
   Number of distributed RAM:   0 (0 LUT4s)
   Number of ripple logic:     68 (136 LUT4s)
   Number of shift registers:   0
   Total number of LUT4s:     719
   Number of PIO sites used: 55 out of 100 (55%)
   Number of PIO FIXEDDELAY:    0
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of 3-state buffers:   0
   Number of PLLs:  0 out of 2 (0%)
   Number of block RAMs:  0 out of 9 (0%)
   Number of CLKDIVs:  0 out of 2 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.

   Number Of Mapped DSP Components:
   --------------------------------
   MULT36X36B          0
   MULT18X18B          0
   MULT18X18MACB       0
   MULT18X18ADDSUBB    0
   MULT18X18ADDSUBSUMB 0
   MULT9X9B            0
   MULT9X9ADDSUBB      0
   MULT9X9ADDSUBSUMB   0
   --------------------------------
   Number of Used DSP Sites:  0 out of 24 (0 %)
   Number of clocks:  1
     Net SysCLK_in_c: 130 loads, 130 rising, 0 falling (Driver: PIO SysCLK_in )

   Number of Clock Enables:  15
     Net Seg7_Counter_1_sqmuxa_i: 6 loads, 6 LSLICEs
     Net u_TxBlock_TxReady_1_sqmuxa_i: 7 loads, 6 LSLICEs
     Net u_TxBlock/un17_edge_txclk: 4 loads, 4 LSLICEs
     Net u_TxBlock/un28_edge_txclk: 1 loads, 1 LSLICEs
     Net u_TxBlock/TxShiftEnable_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net u_mdl_WaveGen/AddressStep_adder_1_sqmuxa_i: 7 loads, 7 LSLICEs
     Net u_PUSHSW_sync/u_SW4/reg_MASK_cnt_enb_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW4/N_11_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW3/reg_MASK_cnt_enb_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW3/N_11_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW2/reg_MASK_cnt_enb_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW2/N_11_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW1/reg_MASK_cnt_enb_1_sqmuxa_i: 1 loads, 1 LSLICEs
     Net u_PUSHSW_sync/u_SW1/N_11_i: 1 loads, 1 LSLICEs
     Net Seg7_Counterce_0: 2 loads, 2 LSLICEs
   Number of local set/reset loads for net nSysRST_in_c merged into GSR:  39
   Number of LSRs:  1
     Net nSysRST_in_c: 44 loads, 40 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_6: 148 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_7: 126 loads
     Net VCC: 105 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_3: 84 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_5: 82 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_2: 78 loads
     Net nSysRST_in_c: 68 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_1: 52 loads
     Net u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_4: 52 loads
     Net u_mdl_WaveGen/AddressStep_adder_14: 26 loads




   Number of warnings:  1
   Number of errors:    0




Design Errors/Warnings

WARNING:  Using local reset signal 'nSysRST_in_c' to infer global GSR net.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+------------+
| IO Name             | Direction | Levelmode | IO         | FIXEDDELAY |
|                     |           |  IO_TYPE  | Register   |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_1   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SysCLK_in           | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| nTxD_Ready          | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+

| TxD_out             | OUTPUT    | LVCMOS25  | OUT        |            |
+---------------------+-----------+-----------+------------+------------+
| nDAC_ENB            | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_7          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_6          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_5          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_4          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_3          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_out_2          | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_in_7           | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_in_6           | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_in_5           | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PORT_in_4           | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| DIPSW_in_4          | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| DIPSW_in_3          | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| DIPSW_in_2          | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| DIPSW_in_1          | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| PUSHSW_in_4         | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| PUSHSW_in_3         | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| PUSHSW_in_2         | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| PUSHSW_in_1         | INPUT     | LVCMOS25  | IN         |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_8   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_7   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_6   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_5   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_4   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_3   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_2   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit4_out_1   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+

| SEG7_Digit3_out_8   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_7   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_6   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_5   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_4   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_3   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_2   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit3_out_1   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_8   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_7   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_6   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_5   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_4   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_3   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_2   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit2_out_1   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_8   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_7   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_6   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_5   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_4   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_3   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| SEG7_Digit1_out_2   | OUTPUT    | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+
| nSysRST_in          | INPUT     | LVCMOS25  |            |            |
+---------------------+-----------+-----------+------------+------------+



Removed logic

Signal nSysRST_in_c_i was merged into signal nSysRST_in_c
Signal un56_seg7_counter_s_7_0_S1 undriven or does not drive anything - clipped.
Signal un56_seg7_counter_s_7_0_COUT undriven or does not drive anything -
     clipped.

Signal u_FreqDiv_Seg7/internal_counter_cry_0_S0_0 undriven or does not drive
     anything - clipped.
Signal u_FreqDiv_Seg7/internal_counter_s_0_S1_23 undriven or does not drive
     anything - clipped.
Signal u_FreqDiv_Seg7/internal_counter_s_0_COUT_23 undriven or does not drive
     anything - clipped.
Signal u_FreqDiv_WaveGen/internal_counter_cry_0_S0_0_0 undriven or does not
     drive anything - clipped.
Signal u_FreqDiv_WaveGen/internal_counter_s_0_S1_0_23 undriven or does not drive
     anything - clipped.
Signal u_FreqDiv_WaveGen/internal_counter_s_0_COUT_0_23 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW1/reg_MASK_counter_cry_0_S0_0 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW1/reg_MASK_counter_cry_0_COUT_5 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW2/reg_MASK_counter_cry_0_S0_0_0 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW2/reg_MASK_counter_cry_0_COUT_0_5 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW3/reg_MASK_counter_cry_0_S0_1_0 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW3/reg_MASK_counter_cry_0_COUT_1_5 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW4/reg_MASK_counter_cry_0_S0_2_0 undriven or does not
     drive anything - clipped.
Signal u_PUSHSW_sync/u_SW4/reg_MASK_counter_cry_0_COUT_2_5 undriven or does not
     drive anything - clipped.
Signal u_mdl_WaveGen/un6_addressstep_adder_cry_0_0_S1 undriven or does not drive
     anything - clipped.
Signal u_mdl_WaveGen/un6_addressstep_adder_cry_0_0_S0 undriven or does not drive
     anything - clipped.
Signal u_mdl_WaveGen/un6_addressstep_adder_s_13_0_S1 undriven or does not drive
     anything - clipped.
Signal u_mdl_WaveGen/un6_addressstep_adder_s_13_0_COUT undriven or does not
     drive anything - clipped.
Signal u_TxBlock/u_TxCLKgen/internal_counter_cry_0_S0_1_0 undriven or does not
     drive anything - clipped.
Signal u_TxBlock/u_TxCLKgen/internal_counter_s_0_S1_1_23 undriven or does not
     drive anything - clipped.
Signal u_TxBlock/u_TxCLKgen/internal_counter_s_0_COUT_1_23 undriven or does not
     drive anything - clipped.
Signal un56_seg7_counter_cry_0_0_S1 undriven or does not drive anything -
     clipped.
Signal un56_seg7_counter_cry_0_0_S0 undriven or does not drive anything -
     clipped.
Block nSysRST_in_pad_RNIGEE was optimized away.

GSR Usage
---------

GSR Component:
   The local reset signal 'nSysRST_in_c' of the design has been inferred as
        Global Set Reset (GSR). The reset signal used for GSR control is
        'nSysRST_in_c'.

GSR Property:

   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.

Components on inferred reset domain with GSR Property disabled
--------------------------------------------------------------

These components have the GSR property set to DISABLED and are on the inferred
     reset domain. The components will respond to the reset signal
     'nSysRST_in_c' via the local reset on the component and not the GSR
     component.

Type and number of components of the type:
   Register = 61

Type and instance name of component:
   Register : Seg7_Counter_0
   Register : Seg7_Counter_15
   Register : u_PUSHSW_sync_u_SW1_reg_PUSHSW_syncio_0
   Register : u_TxBlock/u_TxCLKgen/SysOSC_out
   Register : u_mdl_WaveGen/wave_triangle_value_10
   Register : u_mdl_WaveGen/wave_triangle_value_11
   Register : u_mdl_WaveGen/wave_triangle_value_12
   Register : u_mdl_WaveGen/wave_triangle_value_13
   Register : u_mdl_WaveGen/wave_triangle_value_14
   Register : u_mdl_WaveGen/wave_triangle_value_15
   Register : u_mdl_WaveGen/wave_sawtooth_value_10
   Register : u_mdl_WaveGen/wave_sawtooth_value_11
   Register : u_mdl_WaveGen/wave_sawtooth_value_12
   Register : u_mdl_WaveGen/wave_sawtooth_value_13
   Register : u_mdl_WaveGen/wave_sawtooth_value_14
   Register : u_mdl_WaveGen/wave_sawtooth_value_15
   Register : u_mdl_WaveGen/WaveOut_2
   Register : u_mdl_WaveGen/WaveOut_3
   Register : u_mdl_WaveGen/WaveOut_4
   Register : u_mdl_WaveGen/WaveOut_5
   Register : u_mdl_WaveGen/WaveOut_6
   Register : u_mdl_WaveGen/WaveOut_7
   Register : u_PUSHSW_sync/u_SW4/reg_PUSHSW_sync_1
   Register : u_PUSHSW_sync/u_SW4/reg_PUSHSW_sync_2
   Register : u_PUSHSW_sync/u_SW4/reg_PUSHSW_sync_3
   Register : u_PUSHSW_sync/u_SW4/reg_MASK_cnt_enb
   Register : u_PUSHSW_sync/u_SW4/PUSHSW_H_edge
   Register : u_PUSHSW_sync/u_SW3/reg_PUSHSW_sync_1
   Register : u_PUSHSW_sync/u_SW3/reg_PUSHSW_sync_2
   Register : u_PUSHSW_sync/u_SW3/reg_PUSHSW_sync_3
   Register : u_PUSHSW_sync/u_SW3/reg_MASK_cnt_enb
   Register : u_PUSHSW_sync/u_SW3/PUSHSW_H_edge
   Register : u_PUSHSW_sync/u_SW2/reg_PUSHSW_sync_1
   Register : u_PUSHSW_sync/u_SW2/reg_PUSHSW_sync_2
   Register : u_PUSHSW_sync/u_SW2/reg_PUSHSW_sync_3
   Register : u_PUSHSW_sync/u_SW2/reg_MASK_cnt_enb
   Register : u_PUSHSW_sync/u_SW2/PUSHSW_H_edge
   Register : u_PUSHSW_sync/u_SW1/reg_PUSHSW_sync_1
   Register : u_PUSHSW_sync/u_SW1/reg_PUSHSW_sync_2
   Register : u_PUSHSW_sync/u_SW1/reg_PUSHSW_sync_3
   Register : u_PUSHSW_sync/u_SW1/reg_MASK_cnt_enb
   Register : u_PUSHSW_sync/u_SW1/PUSHSW_H_edge
   Register : u_FreqDiv_WaveGen/SysOSC_out
   Register : u_FreqDiv_Seg7/SysOSC_out

   Register : u_PUSHSW_sync_u_SW4_reg_PUSHSW_syncio_0
   Register : u_PUSHSW_sync_u_SW3_reg_PUSHSW_syncio_0
   Register : u_PUSHSW_sync_u_SW2_reg_PUSHSW_syncio_0
   Register : Seg7_Counter_1
   Register : Seg7_Counter_2
   Register : Seg7_Counter_3
   Register : Seg7_Counter_4
   Register : Seg7_Counter_5
   Register : Seg7_Counter_6
   Register : Seg7_Counter_7
   Register : Seg7_Counter_8
   Register : Seg7_Counter_9
   Register : Seg7_Counter_10
   Register : Seg7_Counter_11
   Register : Seg7_Counter_12
   Register : Seg7_Counter_13
   Register : Seg7_Counter_14

Run Time and Memory Usage
-------------------------

   Total CPU Time: 1 secs
   Total REAL Time: 2 secs
   Peak Memory Usage: 49 MB



































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Copyright (c) 1995
     AT&T Corp.   All rights reserved.
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Copyright (c) 2001 Agere Systems
     All rights reserved.
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     Corporation,  All rights reserved.



Generated from the file 'E:\MFPGA_LAT\top.mrp'