Place & Route TRACE Report
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Lattice TRACE Report - Setup, Version ispLever_v72_PROD_Build (44)
Sun Apr 26 01:06:27 2009

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2008 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce.exe -v 1 -o top.twr top.ncd top.prf 
Design file:     top.ncd
Preference file: top.prf
Device,speed:    LFXP2-5E,6
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • FREQUENCY NET "SysCLK_in_c" 227.635000 MHz (1596 errors)
  • 4096 items scored, 1596 timing errors detected. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "SysCLK_in_c" 227.635000 MHz ; 4096 items scored, 1596 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.163ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u_mdl_WaveGen/AddressStep_adder_2 (from SysCLK_in_c +) Destination: FF Data in u_mdl_WaveGen/u_mdl_sintable/rom_data_11 (to SysCLK_in_c +) Delay: 7.478ns (31.9% logic, 68.1% route), 10 logic levels. Constraint Details: 7.478ns physical path delay u_mdl_WaveGen/SLICE_154 to u_mdl_WaveGen/u_mdl_sintable/SLICE_165 exceeds 4.392ns delay constraint less 0.000ns skew and 0.077ns DIN_SET requirement (totaling 4.315ns) by 3.163ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 R14C17A.CLK to R14C17A.Q0 u_mdl_WaveGen/SLICE_154 (from SysCLK_in_c) ROUTE 3 0.992 R14C17A.Q0 to R14C19B.C0 u_mdl_WaveGen/AddressStep_adder_2 CTOF_DEL --- 0.238 R14C19B.C0 to R14C19B.F0 u_mdl_WaveGen/u_mdl_sintable/SLICE_485 ROUTE 24 1.098 R14C19B.F0 to R20C18D.B1 u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_0 CTOOFX_DEL --- 0.399 R20C18D.B1 to R20C18D.OFX0 u_mdl_WaveGen/u_mdl_sintable/SLICE_307 ROUTE 1 0.000 R20C18D.OFX0 to R20C18D.FXA u_mdl_WaveGen/u_mdl_sintable/sin_out512_11_1_0_0_f5a FXTOOFX_DE --- 0.145 R20C18D.FXA to R20C18D.OFX1 u_mdl_WaveGen/u_mdl_sintable/SLICE_307 ROUTE 1 0.000 R20C18D.OFX1 to R20C18C.FXA u_mdl_WaveGen/u_mdl_sintable/sin_out512_11_1_0_f5a FXTOOFX_DE --- 0.145 R20C18C.FXA to R20C18C.OFX1 u_mdl_WaveGen/u_mdl_sintable/SLICE_308 ROUTE 1 0.000 R20C18C.OFX1 to R20C18A.FXB u_mdl_WaveGen/u_mdl_sintable/sin_out512_11_1_f5b FXTOOFX_DE --- 0.145 R20C18A.FXB to R20C18A.OFX1 SLICE_310 ROUTE 1 1.003 R20C18A.OFX1 to R17C17C.D1 u_mdl_WaveGen/u_mdl_sintable/sin_out512_11 CTOF_DEL --- 0.238 R17C17C.D1 to R17C17C.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_469 ROUTE 1 0.545 R17C17C.F1 to R18C17B.D1 u_mdl_WaveGen/u_mdl_sintable/rom_data_RNO_10_11 CTOF_DEL --- 0.238 R18C17B.D1 to R18C17B.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_429 ROUTE 1 0.708 R18C17B.F1 to R17C17D.A1 u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_0_11 CTOF_DEL --- 0.238 R17C17D.A1 to R17C17D.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_435 ROUTE 1 0.745 R17C17D.F1 to R16C16A.D1 u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_9_11 CTOF_DEL --- 0.238 R16C16A.D1 to R16C16A.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_165 ROUTE 1 0.000 R16C16A.F1 to R16C16A.DI1 u_mdl_WaveGen/u_mdl_sintable/N_961_i (to SysCLK_in_c) -------- 7.478 (31.9% logic, 68.1% route), 10 logic levels. Clock Skew Details: Source Clock: Delay Connection 2.373ns 65.PADDI to R14C17A.CLK Destination Clock Path: Destination Clock: Delay Connection 2.373ns 65.PADDI to R16C16A.CLK Warning: 132.363MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "SysCLK_in_c" 227.635000 | | | MHz ; | 227.635 MHz| 132.363 MHz| 10 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- u_mdl_WaveGen/u_mdl_sintable/sin_out_10 | 1| 993| 62.22% | | | u_mdl_WaveGen/AddressStep_adder_14 | 26| 782| 49.00% | | | u_mdl_WaveGen/u_mdl_sintable/N_961_i | 1| 398| 24.94% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 10_10 | 1| 347| 21.74% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_6 | 148| 316| 19.80% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 5_10 | 1| 305| 19.11% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_7 | 126| 266| 16.67% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 6_10 | 1| 265| 16.60% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 9_11 | 1| 237| 14.85% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 1_10 | 2| 212| 13.28% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_3 | 84| 182| 11.40% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out1024| | | _10_RNICHU3 | 1| 174| 10.90% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_5 | 82| 172| 10.78% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 8_10 | 1| 166| 10.40% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_2 | 78| 166| 10.40% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out1024| | | _10 | 1| 160| 10.03% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: SysCLK_in_c Source: SysCLK_in.PAD Loads: 130 Covered under: FREQUENCY NET "SysCLK_in_c" 227.635000 MHz ; Timing summary: --------------- Timing errors: 1596 Score: 2575368 Cumulative negative slack: 2575368 Constraints cover 5336 paths, 1 nets, and 2512 connections (88.9% coverage) -------------------------------------------------------------------------------- Generated from the file 'E:\MFPGA_LAT\top.twr'