PAR: Place And Route ispLever_v72_PROD_Build (44).
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2008 Lattice Semiconductor Corporation,  All rights reserved.
Sun Apr 26 01:04:50 2009

D:/ispTOOLS7_2_STRT/ispfpga\bin\nt\par -f top.p2t top_map.ncd top.dir top.prf

Preference file: top.prf.

Cost Table Summary
Level/      Number      Timing      Run         NCD
Cost [ncd]  Unrouted    Score       Time        Status
----------  --------    --------    -----       ------------
5_1   *     0           2575368     01:09       Complete        


* : Design saved.

par done!

Lattice Place and Route Report for Design "top_map.ncd"
Sun Apr 26 01:04:50 2009


Best Par Run
PAR: Place And Route ispLever_v72_PROD_Build (44).
Command line: D:/ispTOOLS7_2_STRT/ispfpga\bin\nt\par -f top.p2t top_map.ncd top.dir top.prf
Preference file: top.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file top_map.ncd.
Design name: Module_TOP
NCD version: 3.2
Vendor:      LATTICE
Device:      LFXP2-5E
Package:     TQFP144
Speed:       6
Loading device for application par from file 'mg5a26x29.nph' in
environment: D:/ispTOOLS7_2_STRT/ispfpga.
Package: Version 1.42, Status: FINAL
Speed Hardware Data: version 7.3 (final) 
License checked out.


Ignore Preference Error(s):  True
Dumping design to file C:/TEMP/neo_2.

Device utilization summary:

   GSR                1/1           100% used
   IOLOGIC            6/196           3% used
   PIO (prelim)      55/174          31% used
                     55/100          55% bonded
   SLICE            472/2376         19% used



Number of Signals: 1115
Number of Connections: 2825

Pin Constraint Summary:
   55 out of 55 pins locked (100% locked).

The following 1 signal is selected to use the primary clock routing resources:
    SysCLK_in_c (driver: SysCLK_in, clk load #: 130)

WARNING - par: Signal "SysCLK_in_c" is selected to use Primary clock
          resources; however its driver comp "SysCLK_in" is located at "65",
          which is not a dedicated pin for connecting to Primary clock
          resources.  General routing has to be used to route this signal,
          and it may suffer from excessive delay or skew.
No signal is selected as DCS clock.

The following 1 signal is selected to use the secondary clock routing resources:
    nSysRST_in_c (driver: nSysRST_in, clk load #: 0, sr load #: 44, ce load #: 0)

WARNING - par: Signal "nSysRST_in_c" is selected to use Secondary clock
          resources; however its driver comp "nSysRST_in" is located at
          "48", which is not a dedicated pin for connecting to Secondary
          clock resources.  General routing has to be used to route this
          signal, and it may suffer from excessive delay or skew.
Signal nSysRST_in_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 7 secs 

CDP(congestion driven placement) auto mode does not turn on CDP.
	To force CDP on, set -exp parCDP=1
Starting Placer Phase 1.
Placer score = 8890183.
........................
Placer score = 2933632.
Finished Placer Phase 1.  REAL time: 11 secs 

Starting Placer Phase 2.
.
Placer score =  2799287
Finished Placer Phase 2.  REAL time: 11 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 2 out of 196 (1%)
  PLL        : 0 out of 2 (0%)
  DCS        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "SysCLK_in_c" from comp "SysCLK_in" on PIO site "65 (PB26A)", clk load = 130
  SECONDARY "nSysRST_in_c" from comp "nSysRST_in" on PIO site "48 (PB14B)", clk load = 0, ce load = 0, sr load = 44

  PRIMARY  : 1 out of 8 (12%)
     DCS   : 0 out of 2 (0%)
  SECONDARY: 1 out of 4 (25%)

Edge Clocks:
  No edge clock selected




I/O Usage Summary (final):
   55 out of 174 (31.6%) PIO sites used.
   55 out of 100 (55.0%) bonded PIO sites used.
   Number of PIO comps: 55; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
----------+------------------+-------+-----------------
 I/O Bank | Usage            | Vccio |  Vref1 / Vref2
----------+------------------+-------+-----------------
    0     |  11 / 20  ( 55%) | 2.5V  |      - / -     
    1     |   6 / 6   (100%) | 2.5V  |      - / -     
    2     |  11 / 18  ( 61%) | 2.5V  |      - / -     
    3     |   2 / 4   ( 50%) | 2.5V  |      - / -     
    4     |   8 / 8   (100%) | 2.5V  |      - / -     
    5     |  14 / 18  ( 77%) | 2.5V  |      - / -     
    6     |   3 / 8   ( 37%) | 2.5V  |      - / -     
    7     |   0 / 18  (  0%) |    -  |      - / -     
----------+------------------+-------+-----------------


DSP Utilization Summary:
-------------------------------------
DSP Block #:              1 2 3
# of MULT36X36B                
# of MULT18X18B                
# of MULT18X18MACB             
# of MULT18X18ADDSUBB          
# of MULT18X18ADDSUBSUMB       
# of MULT9X9B                  
# of MULT9X9ADDSUBB            
# of MULT9X9ADDSUBSUMB         

Total placer CPU time: 10 secs 

Dumping design to file top.dir/5_1.ncd.

0 connections routed; 2825 unrouted.
Starting router resource preassignment
WARNING - par: The driver of primary clock net SysCLK_in_c is not placed on
          one of the PIO sites which are dedicated for primary clocks.  This
          primary clock will be routed to a H-spine through general routing
          resource or be routed as secondary clock and may suffer from
          excessive delay or skew.
Completed router resource preassignment. Real time: 13 secs 

Congestion Driven Router (CDR) is turned on.
CDR effort level is set at 0.
To turn CDR off, please set "-exp parCDR=0" on command line.

Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
2825 successful; 0 unrouted; (2598369) real time: 24 secs 
Dumping design to file top.dir/5_1.ncd.
End of iteration 2
2825 successful; 0 unrouted; (2595186) real time: 32 secs 
Dumping design to file top.dir/5_1.ncd.
End of iteration 3
2825 successful; 0 unrouted; (2595186) real time: 40 secs 
End of iteration 4
2825 successful; 0 unrouted; (2595186) real time: 50 secs 
End of iteration 5
2825 successful; 0 unrouted; (2595132) real time: 56 secs 
Dumping design to file top.dir/5_1.ncd.
End of iteration 6
2825 successful; 0 unrouted; (2575368) real time: 1 mins 9 secs 
Dumping design to file top.dir/5_1.ncd.
Total CPU time 1 mins 2 secs 
Total REAL time: 1 mins 9 secs 
Completely routed.
End of route.  2825 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.
Timing score: 2575368 

Total REAL time to completion: 1 mins 9 secs 


All signals are completely routed.


par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2008 Lattice Semiconductor Corporation,  All rights reserved.



Generated from the file 'E:\MFPGA_LAT\top.par'