Build Database Report ngdbuild: version ispLever_v72_PROD_Build (44) Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. Reading 'Module_TOP.ngo' ... Loading NGL library 'D:/ispTOOLS7_2_STRT/ispfpga/mg5a00/data/mg5alib.ngl'... Loading NGL library 'D:/ispTOOLS7_2_STRT/ispfpga/ep5a00/data/ep5alib.ngl'... Loading NGL library 'D:/ispTOOLS7_2_STRT/ispfpga/ep5g00/data/ep5glib.ngl'... Loading NGL library 'D:/ispTOOLS7_2_STRT/ispfpga/or5g00/data/orc5glib.ngl'... Running DRC... WARNING - ngdbuild: logical net 'u_TxBlock/u_TxCLKgen/internal_counter_s_0_COUT_1_23' has no load WARNING - ngdbuild: logical net 'u_TxBlock/u_TxCLKgen/internal_counter_s_0_S1_1_23' has no load WARNING - ngdbuild: logical net 'u_TxBlock/u_TxCLKgen/internal_counter_cry_0_S0_1_0' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW4/reg_MASK_counter_cry_0_COUT_2_5' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW4/reg_MASK_counter_cry_0_S0_2_0' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW3/reg_MASK_counter_cry_0_COUT_1_5' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW3/reg_MASK_counter_cry_0_S0_1_0' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW2/reg_MASK_counter_cry_0_COUT_0_5' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW2/reg_MASK_counter_cry_0_S0_0_0' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW1/reg_MASK_counter_cry_0_COUT_5' has no load WARNING - ngdbuild: logical net 'u_PUSHSW_sync/u_SW1/reg_MASK_counter_cry_0_S0_0' has no load WARNING - ngdbuild: logical net 'u_mdl_WaveGen/un6_addressstep_adder_s_13_0_COUT' has no load WARNING - ngdbuild: logical net 'u_mdl_WaveGen/un6_addressstep_adder_s_13_0_S1' has no load WARNING - ngdbuild: logical net 'u_mdl_WaveGen/un6_addressstep_adder_cry_0_0_S0' has no load WARNING - ngdbuild: logical net 'u_mdl_WaveGen/un6_addressstep_adder_cry_0_0_S1' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_WaveGen/internal_counter_s_0_COUT_0_23' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_WaveGen/internal_counter_s_0_S1_0_23' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_WaveGen/internal_counter_cry_0_S0_0_0' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_Seg7/internal_counter_s_0_COUT_23' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_Seg7/internal_counter_s_0_S1_23' has no load WARNING - ngdbuild: logical net 'u_FreqDiv_Seg7/internal_counter_cry_0_S0_0' has no load WARNING - ngdbuild: logical net 'un56_seg7_counter_cry_0_0_S0' has no load WARNING - ngdbuild: logical net 'un56_seg7_counter_cry_0_0_S1' has no load WARNING - ngdbuild: logical net 'un56_seg7_counter_s_7_0_S1' has no load WARNING - ngdbuild: logical net 'un56_seg7_counter_s_7_0_COUT' has no load WARNING - ngdbuild: DRC complete with 25 warnings Design Results: 735 blocks expanded complete the first expansion Writing 'top.ngd' ... Generated from the file 'E:\MFPGA_LAT\top.drp'