-------------------------------------------------------------------------------- Lattice TRACE Report - Setup, Version ispLever_v72_PROD_Build (44) Sun Apr 26 01:04:48 2009 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -o checkpnt.twr top_map.ncd top.prf Design file: top_map.ncd Preference file: top.prf Device,speed: LFXP2-5E,6 Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference SummaryFREQUENCY NET "SysCLK_in_c" 227.635000 MHz (2227 errors) 4096 items scored, 2227 timing errors detected. Warning: 123.900MHz is the maximum frequency for this preference. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "SysCLK_in_c" 227.635000 MHz ; 4096 items scored, 2227 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.679ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q u_mdl_WaveGen/AddressStep_adder_5 (from SysCLK_in_c +) Destination: FF Data in u_mdl_WaveGen/u_mdl_sintable/rom_data_10 (to SysCLK_in_c +) Delay: 7.994ns (31.9% logic, 68.1% route), 10 logic levels. Constraint Details: 7.994ns physical path delay u_mdl_WaveGen/SLICE_155 to u_mdl_WaveGen/u_mdl_sintable/SLICE_165 exceeds 4.392ns delay constraint less 0.077ns DIN_SET requirement (totaling 4.315ns) by 3.679ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.363 *SLICE_155.CLK to */SLICE_155.Q1 u_mdl_WaveGen/SLICE_155 (from SysCLK_in_c) ROUTE 2 e 0.907 */SLICE_155.Q1 to */SLICE_404.A1 u_mdl_WaveGen/AddressStep_adder_5 CTOF_DEL --- 0.238 */SLICE_404.A1 to */SLICE_404.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_404 ROUTE 84 e 0.907 */SLICE_404.F1 to */SLICE_386.B0 u_mdl_WaveGen/u_mdl_sintable/sin_table_adrs_3 CTOOFX_DEL --- 0.399 */SLICE_386.B0 to *LICE_386.OFX0 u_mdl_WaveGen/u_mdl_sintable/SLICE_386 ROUTE 1 e 0.001 *LICE_386.OFX0 to *SLICE_385.FXB u_mdl_WaveGen/u_mdl_sintable/sin_out1024_10_1_1_1_f5b FXTOOFX_DE --- 0.145 *SLICE_385.FXB to *LICE_385.OFX1 u_mdl_WaveGen/u_mdl_sintable/SLICE_385 ROUTE 1 e 0.001 *LICE_385.OFX1 to *SLICE_384.FXB u_mdl_WaveGen/u_mdl_sintable/sin_out1024_10_1_1_f5b FXTOOFX_DE --- 0.145 *SLICE_384.FXB to *LICE_384.OFX1 u_mdl_WaveGen/u_mdl_sintable/SLICE_384 ROUTE 1 e 0.001 *LICE_384.OFX1 to *SLICE_386.FXB u_mdl_WaveGen/u_mdl_sintable/sin_out1024_10_1_f5b FXTOOFX_DE --- 0.145 *SLICE_386.FXB to *LICE_386.OFX1 u_mdl_WaveGen/u_mdl_sintable/SLICE_386 ROUTE 1 e 0.907 *LICE_386.OFX1 to */SLICE_428.A1 u_mdl_WaveGen/u_mdl_sintable/sin_out1024_10 CTOF_DEL --- 0.238 */SLICE_428.A1 to */SLICE_428.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_428 ROUTE 1 e 0.907 */SLICE_428.F1 to */SLICE_426.A1 u_mdl_WaveGen/u_mdl_sintable/sin_out1024_10_RNICHU3 CTOF_DEL --- 0.238 */SLICE_426.A1 to */SLICE_426.F1 u_mdl_WaveGen/u_mdl_sintable/SLICE_426 ROUTE 2 e 0.907 */SLICE_426.F1 to */SLICE_174.A0 u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_1_10 CTOOFX_DEL --- 0.399 */SLICE_174.A0 to *LICE_174.OFX0 u_mdl_WaveGen/u_mdl_sintable/rom_data_RNO_1_10/SLICE_174 ROUTE 1 e 0.907 *LICE_174.OFX0 to */SLICE_165.B0 u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_5_10 CTOF_DEL --- 0.238 */SLICE_165.B0 to */SLICE_165.F0 u_mdl_WaveGen/u_mdl_sintable/SLICE_165 ROUTE 1 e 0.001 */SLICE_165.F0 to *SLICE_165.DI0 u_mdl_WaveGen/u_mdl_sintable/sin_out_10 (to SysCLK_in_c) -------- 7.994 (31.9% logic, 68.1% route), 10 logic levels. Warning: 123.900MHz is the maximum frequency for this preference. Report Summary ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "SysCLK_in_c" 227.635000 | | | MHz ; | 227.635 MHz| 123.900 MHz| 10 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- u_mdl_WaveGen/u_mdl_sintable/sin_out_10 | 1| 994| 44.63% | | | u_mdl_WaveGen/AddressStep_adder_14 | 26| 762| 34.22% | | | u_mdl_WaveGen/u_mdl_sintable/N_961_i | 1| 377| 16.93% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 10_10 | 1| 348| 15.63% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_6 | 148| 316| 14.19% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 5_10 | 1| 308| 13.83% | | | u_TxBlock/u_TxCLKgen/internal_counterZ0Z| | | _22 | 2| 288| 12.93% | | | u_TxBlock/u_TxCLKgen/internal_counter | 24| 288| 12.93% | | | u_mdl_WaveGen/u_mdl_sintable/sin_table_a| | | drs_7 | 126| 266| 11.94% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 6_10 | 1| 264| 11.85% | | | u_mdl_WaveGen/u_mdl_sintable/sin_out_iv_| | | 9_11 | 1| 230| 10.33% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: SysCLK_in_c Source: SysCLK_in.PAD Loads: 130 Covered under: FREQUENCY NET "SysCLK_in_c" 227.635000 MHz ; Timing summary: Timing errors: 2227 Score: 3748176 Cumulative negative slack: 3748176 Constraints cover 5336 paths, 1 nets, and 2451 connections (86.8% coverage) -------------------------------------------------------------------------------- Generated from the file 'E:\MFPGA_LAT\top.tw1'