#-- Synopsys, Inc.
#-- Version 9.6L2
#-- Project file C:\marutsu\fpga\mfpga_lat\run_options.txt
#-- Written on Tue May 19 15:09:13 2009


#add_file options
add_file -vhdl -lib work "C:/ispTOOLS7_2_STRT/ispcpld/../cae_library/synthesis/vhdl/XP2.vhd"
add_file -vhdl -lib work "./hdl/mod_freq_div.vhd"
add_file -vhdl -lib work "./hdl/sintable.vhd"
add_file -vhdl -lib work "./hdl/mod_pushsw_sync.vhd"
add_file -vhdl -lib work "./hdl/mod_7seg.vhd"
add_file -vhdl -lib work "./hdl/mod_uart_tx.vhd"
add_file -vhdl -lib work "./hdl/mod_wavegen.vhd"
add_file -vhdl -lib work "./hdl/mod_pushsw_sync4.vhd"
add_file -vhdl -lib work "./hdl/mod_7seg_x4.vhd"
add_file -vhdl -lib work "./hdl/mod_top.vhd"


#implementation: "mfpga_lat"
impl -add mfpga_lat -type fpga

#device options
set_option -technology LATTICE-XP2
set_option -part LFXP2_5E
set_option -package M132C
set_option -speed_grade -5
set_option -part_companion ""

#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -top_module "work.Module_TOP"

#map options
set_option -frequency 200.000
set_option -vendor_xcompatible_mode 0
set_option -vendor_xcompatible_mode 0
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
set_option -force_gsr false
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 0

#set result format/file last
project -result_file "./Module_TOP.edi"

#set log file 
set_option log_file "C:/marutsu/fpga/mfpga_lat/module_top.srf" 

#
#implementation attributes

set_option -vlog_std v2001
set_option -num_critical_paths 3
set_option -num_startend_points 0
set_option -dup false
set_option -compiler_compatible true
set_option -auto_constrain_io true
impl -active "mfpga_lat"
