
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   01:28:39 03/27/2009
-- Design Name:   Module_TxBlock
-- Module Name:   E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_TxBlock.vhd
-- Project Name:  MFPGA_XIL
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Module_TxBlock
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tst_TxBlock_vhd IS
	generic (
		tCYC	: time	:= 100 ns ;
		tCYC2	: time	:= 1 us ;
		tPD		: time	:= 7 ns
	) ;
END tst_TxBlock_vhd;

ARCHITECTURE behavior OF tst_TxBlock_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT Module_TxBlock
	PORT(
		SysCLK_in : IN std_logic;
		SysRST_in : IN std_logic;
		TxDataWen_i : IN std_logic;
		TxData_i : IN std_logic_vector(7 downto 0);          
		TxD_o : OUT std_logic;
		TxRdy_o : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL SysCLK_in :  std_logic := '1';
	SIGNAL SysRST_in :  std_logic := '1';
	SIGNAL TxDataWen_i :  std_logic := '0';
	SIGNAL TxData_i :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL TxD_o :  std_logic;
	SIGNAL TxRdy_o :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: Module_TxBlock PORT MAP(
		SysCLK_in => SysCLK_in,
		SysRST_in => SysRST_in,
		TxDataWen_i => TxDataWen_i,
		TxData_i => TxData_i,
		TxD_o => TxD_o,
		TxRdy_o => TxRdy_o
	);

ClockGen : process
begin
	wait for (tCYC/2) ;
		SysCLK_in	<= not SysCLK_in ;
end process ;

Tb : process
begin
	wait for tPD ;
	wait for (tCYC*2) ;
		SysRST_in	<= '0' ;
	wait for (tCYC*2) ;
		TxData_i	<= x"81" ;
	wait for (tCYC*2) ;
		TxDataWen_i	<= '1' ;
	wait for (tCYC*5) ;
		TxData_i	<= x"00" ;
		TxDataWen_i	<= '0' ;

	wait for 120 us ;
	wait for (tCYC*2) ;
		TxData_i	<= x"18" ;
	wait for (tCYC*2) ;
		TxDataWen_i	<= '1' ;
	wait for (tCYC*5) ;
		TxData_i	<= x"00" ;
		TxDataWen_i	<= '0' ;

	wait ;

end process ;


END;
