MFPGA_XIL Project Status
Project File: | MFPGA_XIL.ise | Current State: | Placed and Routed
Module Name: | Module_WaveGenerator | Errors: | No Errors
Target Device: | xc3s250e-4vq100 | Warnings: | 18 Warnings
Product Version: | ISE 9.2.04i | Updated: | ? 3 17 02:11:53 2009

MFPGA_XIL Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Flip Flops | 44 | 4,896 | 1% |
Number of 4 input LUTs | 63 | 4,896 | 1% |
Logic Distribution |  |  |  |
Number of occupied Slices | 43 | 2,448 | 1% |
Number of Slices containing only related logic | 43 | 43 | 100% |
Number of Slices containing unrelated logic | 0 | 43 | 0% |
Total Number of 4 input LUTs | 82 | 4,896 | 1% |
Number used as logic | 63 |  |  |
Number used as a route-thru | 19 |  |  |
Number of bonded IOBs | 21 | 66 | 31% |
IOB Flip Flops | 8 |  |  |
Number of Block RAMs | 2 | 12 | 16% |
Number of GCLKs | 1 | 24 | 4% |
Total equivalent gate count for design | 132,127 |  |  |
Additional JTAG gate count for IOBs | 1,008 |  |  |

Performance Summary
Final Timing Score: | 0 | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | ? 3 17 02:11:19 2009 | 0 | 18 Warnings | 2 Infos
Translation Report | Current | ? 3 17 02:11:34 2009 | 0 | 0 | 0
Map Report | Current | ? 3 17 02:11:41 2009 | 0 | 0 | 3 Infos
Place and Route Report | Current | ? 3 17 02:11:51 2009 | 0 | 0 | 2 Infos
Static Timing Report | Current | ? 3 17 02:11:53 2009 | 0 | 0 | 3 Infos
Bitgen Report |  |  |  |  |