# Reading C:/Modeltech_6.2c/tcl/vsim/pref.tcl 
# do {tst_mdl_WaveGen_vhd.fdo} 
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_sintable
# -- Compiling architecture behavioral of module_sintable
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
# ** Error: tst_mdl_WaveGen.vhd(82): near "tb": expecting: PROCESS
# ** Error: C:/Modeltech_6.2c/win32/vcom failed.
# Error in macro ./tst_mdl_WaveGen_vhd.fdo line 7
# C:/Modeltech_6.2c/win32/vcom failed.
#     while executing
# "vcom -explicit  -93 "tst_mdl_WaveGen.vhd""
do {tst_mdl_WaveGen_vhd.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_sintable
# -- Compiling architecture behavioral of module_sintable
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
# vsim -lib work -t 1ps tst_mdl_WaveGen_vhd 
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
# .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# .main_pane.workspace.interior.cs.nb.canvas.notebook.cs.page2.cs
# .main_pane.signals.interior.cs
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
add wave -0r *
# Unrecognized option: "-0r" ignored.
add wave -r *
restart
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
run 10 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 10 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_mdl_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 1 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 10 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
# ** Error: E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd(146): near "if": expecting: PROCESS
# C:/Modeltech_6.2c/win32/vcom failed.
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity module_wavegenerator
# -- Compiling architecture behavioral of module_wavegenerator
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 10 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
run 20 us
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/wave_old.do
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_mdl_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 200 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf vsim
# WLF Error: File is open by another application or was not closed properly.
# Cannot open file: E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf
compare start vsim sim
# Dataset not open: vsim
compare options -track
# compare options failed:  No compare session started.
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/wave_old.do
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf vsim
# WLF Error: File is open by another application or was not closed properly.
# Cannot open file: E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf vsim
# WLF Error: File is open by another application or was not closed properly.
# Cannot open file: E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim.wlf
compare start vsim vsim
# Dataset not open: vsim
compare add -recursive -all -wave *
# compare add failed:  No compare session started.
# A compare must be started before adding compare signals.
compare run
# compare run failed:  No compare session started.
# A compare must be started before running comparison.
write format wave -window .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/wave_old.do
# Optimization canceled
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_mdl_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 200 us
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf vsim_0x40
# E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf opened as dataset "vsim_0x40"
compare start vsim_0x40 sim
compare options -track
compare see -prevanno -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -first -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -first -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -prevanno -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -prevanno -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -nextanno -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare see -nextanno -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# No comparison differences.
compare run
# No signals specified to compare.
compare end
restart
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
run 200 us
# Profiling
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# Profiling paused, 14 samples taken (7% in user code)
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf vsim_0x40
# E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf opened as dataset "vsim_0x40"
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x60.wlf vsim_0x60
# E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x60.wlf opened as dataset "vsim_0x60"
compare start vsim_0x40 vsim_0x60
compare add -recursive -all -wave *
# Created 29 comparisons. 
compare end
view dataflow
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.df.c
vcom -explicit -93 E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_mdl_WaveGen.vhd
# Model Technology ModelSim SE vcom 6.2c Compiler 2006.08 Aug 26 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package numeric_std
# -- Compiling entity tst_mdl_wavegen_vhd
# -- Compiling architecture behavior of tst_mdl_wavegen_vhd
restart
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
# Loading C:\Modeltech_6.2c\win32/libswiftpli.dll
# Loading C:\Modeltech_6.2c\win32/../std.standard
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.std_logic_unsigned(body)
# Loading C:\Modeltech_6.2c\win32/../ieee.numeric_std(body)
# Loading work.tst_mdl_wavegen_vhd(behavior)
# Loading work.module_wavegenerator(behavioral)
# Loading work.module_sintable(behavioral)
run 200  us
# Profiling
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ps  Iteration: 0  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 10 ns  Iteration: 3  Instance: /tst_mdl_wavegen_vhd/uut/u_mdl_sintable
# Profiling paused, 14 samples taken (0% in user code)
quit -sim
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf vsim_0x40
# E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x40.wlf opened as dataset "vsim_0x40"
dataset open E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x60.wlf vsim_0x60
# E:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/vsim_0x60.wlf opened as dataset "vsim_0x60"
compare start vsim_0x40 vsim_0x60
add wave -r *
restart
# No design loaded.  Nothing to restart.
run 
# No Design Loaded!
compare run
# No signals specified to compare.
compare add -wave -tolL {0 ns} -tolT {0 ns} vsim_0x40:/tst_mdl_wavegen_vhd/waveout
# Created 1 comparison. 
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare run
# Computing waveform differences from time 0 ps to 200 us
# 
# Max total difference per signal limit of 100 reached on signal compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\
# Comparison reached signal difference limit at time 4090 ns
# Found 285 differences.
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 2: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 90 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 3: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 130 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 4: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 130 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 5: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 170 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 6: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 170 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 7: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(3) at 170 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 8: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 170 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 9: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 170 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 10: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 210 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 11: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 210 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 12: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 250 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 13: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 250 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 14: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 290 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 15: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(4) at 290 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 16: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(3) at 290 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 17: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 290 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 18: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 290 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 19: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 330 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 20: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 330 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 21: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 330 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 22: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 370 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 23: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(3) at 370 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 24: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 410 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 25: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 410 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 26: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 450 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 27: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 450 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 28: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 29: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 30: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(5) at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 31: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(4) at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 32: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 33: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 490 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 34: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 530 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 35: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 530 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 36: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(3) at 530 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 37: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 570 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 38: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 570 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 39: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 610 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 40: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(2) at 610 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 41: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 610 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 42: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\ at 650 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 43: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(1) at 650 ns delta 2
compare see -next -wavewin .main_pane.mdi.interior.cs.vm.paneset.cli_1.wf.clip.cs.pw.wf
# Diff 44: compare:/tst_mdl_wavegen_vhd/\waveout<>waveout\(0) at 650 ns delta 2
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
compare configure compare:/tst_mdl_wavegen_vhd/\\waveout<>waveout\\ -tolL {0 ns} -tolT {0 ns} -clock none
# 0
