m255
13
cModel Technology
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
T_opt
VX>V45F]L;haZK>^b=NfA11
04 15 8 work tst_txblock_vhd behavior 1
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2c;35
T_opt1
V<C47jKN>K_4JWj?nBRK??3
04 19 8 work tst_mdl_wavegen_vhd behavior 0
o-quiet +acc -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2c;35
Emodule_freq_div
w1238086209
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FHDL/Mod_Freq_div.vhd
l0
L30
Vbc1WgzcfoNRM5SmU=MElH3
OE;C;6.2c;35
31
o-explicit -93
tExplicit 1
Abehavioral
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work module_freq_div bc1WgzcfoNRM5SmU=MElH3
l46
L42
VF@zVSG:@zKi=HV>bcme100
OE;C;6.2c;35
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-explicit -93
tExplicit 1
Emodule_sintable
w1237380890
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FHDL/sintable.vhd
l0
L34
V>dHkFkk[2V1eC6C[Ch`o82
OE;C;6.2c;35
31
o-explicit -93
tExplicit 1
Abehavioral
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work module_sintable >dHkFkk[2V1eC6C[Ch`o82
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
l61
L47
V1XWBz1e2EHUTH6[9Z?@mT0
OE;C;6.2c;35
o-explicit -93
tExplicit 1
Emodule_txblock
w1238087630
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FE:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_UART_Tx.vhd
l0
L25
VX>9?0XkO<]FETBPS5kfO[1
OE;C;6.2c;35
31
o-explicit -93
tExplicit 1
Abehavioral
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work module_txblock X>9?0XkO<]FETBPS5kfO[1
l78
L42
VX:7TGHFPJIQF5_B>Rlf920
OE;C;6.2c;35
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
o-explicit -93
tExplicit 1
Emodule_wavegenerator
w1238355651
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FE:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/HDL/Mod_WaveGen.vhd
l0
L30
VLkm061ZK?j<=SJloN;8<d1
OE;C;6.2c;35
31
o-explicit -93
tExplicit 1
Abehavioral
DE work module_sintable >dHkFkk[2V1eC6C[Ch`o82
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work module_wavegenerator Lkm061ZK?j<=SJloN;8<d1
31
M3 ieee std_logic_1164
M2 ieee std_logic_arith
M1 ieee std_logic_unsigned
l70
L47
VP;0QJ3K[NLB?KlPLMdA@:1
OE;C;6.2c;35
o-explicit -93
tExplicit 1
Etst_mdl_wavegen_vhd
w1238356293
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
31
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FE:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_mdl_WaveGen.vhd
l0
L34
VboAckLdJdOb>G;B237IF=1
OE;C;6.2c;35
o-explicit -93
tExplicit 1
Abehavior
DE work module_wavegenerator Lkm061ZK?j<=SJloN;8<d1
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work tst_mdl_wavegen_vhd boAckLdJdOb>G;B237IF=1
31
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee numeric_std
l65
L41
VCo^dbA1?9AJ9HnAgH?eCm2
OE;C;6.2c;35
o-explicit -93
tExplicit 1
Etst_txblock_vhd
w1238087635
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dE:\usr\Kurusugawa\MARUTSU\FPGA_BaseBoard\FPGA\MMBD\MFPGA_XIL
FE:/usr/Kurusugawa/MARUTSU/FPGA_BaseBoard/FPGA/MMBD/MFPGA_XIL/tst_TxBlock.vhd
l0
L34
VNzmCaGeZLW>0=C1kJA0f;2
OE;C;6.2c;35
31
o-explicit -93
tExplicit 1
Abehavior
DP ieee numeric_std =NSdli^?T5OD8;4F<blj<3
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_unsigned hEMVMlaNCR^<OOoVNV;m90
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work tst_txblock_vhd NzmCaGeZLW>0=C1kJA0f;2
l66
L42
VOnd5NYD`XSXKF5Kfd>Y4l0
OE;C;6.2c;35
31
M4 ieee std_logic_1164
M3 ieee std_logic_unsigned
M2 ieee std_logic_arith
M1 ieee numeric_std
o-explicit -93
tExplicit 1
